The present invention relates generally to computer architectures. More particulary, the invention is directed to systems and methods for interfacing a short word length memory to a significantly wider bus operated in an address/data multiplexing mode.
The power-on-reset cycle used to initialize or boot a computer is prescribed by code usually stored in a non-volatile memory of the computer, typically a programmable read only memory (PROM), a flash ROM or a conventional ROM. For simplicity, the generic term ROM will be used hereinafter to represent all three classes of devices. One of skill in the art will obviously recognize that when the discussion deals with a writing operation the memory under consideration is flash ROM, or even possibly a RAM. A ROM of 0.5M bytes is typically adequate to perform the sequence. The typical commercially available ROM devices suited to this application have data ports of 8 or 16 bits.
The storage in such ROM of information other than initialization or boot code is fully contemplated, though such usage is less likely to occur. The invention will therefore be described in the context of the most likely use.
In contrast to the short word length and slow speed of the ROM devices, computer processors, such as the PowerPC 601 (Trademark of IBM Corporation) processor commercially available from IBM Corporation, use 32-bit address buses and 32/64-bit data. buses and operate at rates typically an order of magnitude faster. The features of this particular processor are described the publication PowerPC 601. Risc Microprocessor Users Manual MPC 601 UM/AD. The relative inadequacy of such ROM devices is also apparent when compared to contemporary system buses designs. An example is the Peripheral Component Interconnect (PCI) bus, as defined in the PCI Local Bus Specification distributed by the PCI Special Interest Group.
A somewhat more subtle but equally real technical problem encountered with the use of a ROM to initialize the aforementioned PowerPC 60l processor arises from the fact that the processor starts in a burst mode. In this mode the processor expects 32-bytes of data in four increments of 8 bytes each. Thus, there is a need to convert 8 or 16-bit ROM data to four increments of 8 byte units. This size corresponds to an L1 cache segment length and can be efficiently transferred using industry standard bus architectures such as the aforementioned PCI bus. Note that a segment in the PowerPC 601 is half a cache line.
Though such boot ROMS could be located on buses architected with fewer than 32-bits, such as the industry standard architecture (ISA) or tlhe extended industry standard architecture (EISA) buses, the bridge and address translations required to get from the ISA bus to the 32-bit PCI bus, and eventually to the 32/64-bit processor bus itself, would entail a significant expenditure of time and resources during any initialization and boot sequence. This is further aggravated by the time needed to translate the address in accessing the ISA or EISA buses.
Therefore, what is needed is a system and method by which a short word length ROM of relatively slow speed can be interfaced to a significantly wider bus to transfer over that bus data directed to a high speed and wide bus processor. These objectives should be attainable using commercially available processors, commercially available ROMs and in tie context of commercially defined system bus architectures.